A. Field of the Invention
The present invention relates generally to address translation, and in particular to apparatus and methods for address translation for communications handled by a bus bridge.
B. Description of the Prior Art
Computer architecture is constantly changing with technological advances and developments of new techniques. As certain elements of computer architecture change, other elements must be adjusted in some manner to compensate for these changes. Sometimes adjustments are made in hardware, sometimes in software, and sometimes in both.
One consistent change in computer architecture has been longer bit-lengths to perform various aspects of processing. Most recently, some architectures have utilized 64-bit lengths for addressing and information transfer. With the advent of 64-bit architectures comes the problem of compatibility between existing 32-bit elements and new 64-bit elements. For example, it is often necessary to transfer information between a 32-bit bus and a 64-bit bus.
When compatibility must be maintained between elements of an architecture, an intermediary device, like a bridge between buses, can adjust incompatibilities between devices. In addition to handling incompatibility issues between devices on each bus, or between the buses, a bridge transfers information. A bridge is frequently used to transfer information between buses and monitors each bus for information intended for the other bus. Upon detecting information on one bus intended for the other bus, the bridge captures the information and takes steps necessary to transfer the information to the destination device or bus. For example, if the elements have different data transfer rates, an intermediary device could perform buffering between the elements in one or both directions to alleviate the rate incompatibility.
For example, a bridge often connects the Peripheral Component Interface (PCI) Local Bus, offering multiplexed address and data lines, and which is a bus architecture designed to form a high-performance, industry standard computer. Details of the PCI Local Bus can be found in The PCI Local Bus 2.1 Specification, which is hereby incorporated by reference as background information.
The PCI has achieved a great deal of popularity with server machines having greater than four gigabytes (GB) of RAM. For such machines, PCI devices should be locatable (i.e., have addresses) above the first 32 bits (4 GB) of address space to avoid conflicts with RAM addresses. The PCI Local Bus 2.1 specification allows this through the use of 64-bit Dual Address Cycles, although the bus does not require support of those cycles. Consequently, pre-2.1 devices and most existing "2.1 compliant" devices cannot support addressing above 4 GB.
Current PCI Bridge devices provide 64-bit to 32-bit address translation in the "downstream" (primary to secondary bus) direction only. This allows 32-bit-only PCI slave devices on the secondary bus to be located arbitrarily within the full 64-bit address space of the primary bus. The 32-bit-only PCI master devices on the secondary bus, however, are confined to addressing only the first 32 bits (4 GB) of the primary bus.
There is a need for apparatus and methods for transferring information between computer elements that address issues of data transfer address width incompatibility.